1. Field of the Invention
The present invention generally relates to the formation of electrically conductive patterns on surfaces and, more particularly, to the formation of conductive patterns and via connections on and through lamina of multi-layer electronic devices.
2. Description of the Prior Art
The use of electrically conductive patterns on insulating substrates has been in widespread use in the construction of electrical and electronic devices for many years. Printed circuit boards and integrated circuit devices are exemplary of such conductor structures and indicate the wide range of sizes at which such conductive patterns can be formed. More recently, so-called multi-layer module (MLM) constructions, including multi-layer ceramic (MLC) modules have been used to provide a large number of interconnections between a plurality of chips contained in a single module. This type of construction is particularly advantageous since it allows many chips, possibly fabricated with mutually incompatible technologies, to be used together in a single electronic component. Circuits of much higher complexity can also be provided than could be integrated on a single chip at acceptable manufacturing yields.
Multi-layer modules are characterized by including a plurality of layers with conductive patterns formed thereon. These layers are generally divided into functional groups for providing power to each chip included therein, providing signal interconnections, shielding and forming connections to the individual chips. This latter group of layers, commonly referred to as distribution wiring, requires particularly fine patterning of conductors. Connections between layers are formed by placing conductive material in "through holes" formed in the insulating layers. Such completed structures are commonly referred to as vias.
The trend toward increasing integration density in integrated circuits has also been followed in multi-layer modules, requiring finer patterns of conductors, particularly in layers of distribution wiring which interface directly with chip terminals. Finer wiring patterns also implies that via patterns must also be formed at reduced size. Increased registration accuracy from layer to layer is also generally required since increasing via density without a scaled reduction in via diameter results in removal of a higher fraction of the lamina material which can make the layer extremely fragile.
Formation of conductive patterns has been done in the past by any one of several methods including the screening of conductive paste through a mask, ink jet writing, decal metallurgy transfer, and electron and laser patterning, each of which has severe limitations. Short usable lifetime of masks for screening or spraying operations increase costs and the minimum feature size available from such masks is limited. Materials which can be sprayed or screened also necessarily include some volatile solvents which must be removed by drying or baking to stabilize the pattern before the layers can be laminated together to form an MLM or MLC structure. Ink jet writing is slow and also limited as to minimum feature size. Decal metallurgy transfer is a complicated multi-step process requiring lithography steps and high registration accuracy. Electron/laser patterning requires substantial instrumentation and complex and expensive equipment. Ideally, photolithography is capable of producing highly conductive patterns of such metals as copper, gold, molybdenum, tungsten, etc. but is also a multi-step process which requires highly reactive etchants which are incompatible with the preferred materials for the insulating lamina of MLM devices.
Electrostatic formation of patterns has also been known and is the basic principle of the electrophotographic process. The same principles are used in virtually all commercially available copiers and laser printers at the present time. In this process, a photoconductor is exposed to an image which is then developed with toner. The toner is then transferred to a substrate such as paper. Typically the toner is a dry, pulverent and non-conductive material. Resolution of about five lines/mm is typically obtained. However, it is known that finer resolution is available from the use of liquid toners. However, the toner used, whether in the form of a liquid or dry powder is non-conductive.
At small pattern feature sizes, registration of layers is also complicated by the materials preferred for the insulating layers of MLM structures and MLC structures, in particular. In MLC structures, the layers are formed of uncured ceramic materials which are referred to as green sheets. These green sheets, at the time of patterning and/or via formation also contain volatile materials which cause slight shrinkage when they are driven off during lamination of the MLC device.
A recent technique of via formation involves the pressing of conductive metal spheres or rods into the green sheet to form vias. However, this requires some means to locate the conductive spheres at the points on the green sheet where vias are to be formed. This is typically done with a sheet including indentations or perforations into which the spheres can be distributed. However, the use of such a structure is unreliable since there is no mechanism for assuring that a sphere will, in fact, be positioned at every desired via location at the time of a pressing operation to embed the spheres in the green sheet. Further, a separate custom sheet must be made for each different via pattern desired, causing substantial expense in a process of limited reliability and manufacturing yield.
It should also be observed that the currently most reliable and preferred methods of forming conductive surface patterns and via patterns require significant amounts of expensive tooling and are therefore generally too expensive for the fabrication of custom MLM or MLC components. Therefore, as a practical matter, the cost of such tooling must be amortized over a large number of identical devices and designs may not be easily altered without the provision of special structures requiring significant space within the module. Conversely, the MLM technology is not realistically available for the construction of custom circuit components.